![]() ![]() We use the MrBayes 3 tool as a framework for designing our co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA)-based co-processor. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. The PLF consists of a loop with no conditional behavior or dependencies between iterations. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. ![]()
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